vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 1 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 low capacitance bidirectional symmetrical (bisy) single line esd-protection diode in silicon package marking (example only) 1 = year code ? open circle = month code and pin 1 ? xy = type code features ? ultra compact clp0603 package ? low package height < 0.3 mm ? 1-line esd-protection ? working range 5.5 v ? low leakage current < 0.1 a ? low load capacitance c d < 0.8 pf ? esd-protection acc. iec 61000-4-2 ? 13 kv contact discharge ? 13 kv air discharge ? lead plating: au (e4) ? lead material: tiniag ? e4 - precious metal (e.g. ag, au, nipd, nipdau) (no sn) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 ? ? ? 0.3 0.27 0.6 22544 22543 xy 1 22454 ordering information device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity vbus05a1-sd0 VBUS05A1-SD0-G4-08 15 000 15 000 package data device name package name type code weight flammability rating moisture sensitivity level soldering conditions vbus05a1-sd0 clp0603 5a 0.12 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals reflow soldering according jedec std-020 absolute maximum ratings parameter test conditions symbol value unit peak pulse current acc. iec 610 00-4-5, 8/20 s/single shot i ppm 2.5 a peak pulse power pin 1 to pin 2 acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 45 w esd immunity contact discharge acc. iec61000-4-2; 10 pulses v esd 13 kv air discharge acc. iec61000-4-2; 10 pulses 13 operating temperature junction temperature t j - 55 to + 150 c storage temperature t stg - 55 to + 150 c
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 2 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 esd-protection for high-speed signal or data lines the vbus05a1-sd0 is a bidirectional and symmetrical (bisy) esd-protection device which clamps positive and negative overvoltage transients to ground. connected between the signal or data line and the ground th e vbus05a1-sd0 offers a high isolation (low leakage current, low capacitance) within the specified working range. due to the short leads and small package size of the tiny clp0603 package the line inductance is very low, so that fast transients like and esd-strike can be clamped with minimal over- or undershoots. due to the very low capacitance the vbus05a1-sd0 can be used for high speed data ports like hdmi, usb 3.0 or thunderbold. typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 ? /150 pf) fig. 2 - 8/20 s peak pulse current wave form acc. iec 61000-4-5 fig. 3 - typical capacitance c d vs. reverse voltage v r fig. 4 - typical reverse voltage v r vs. reverse current i r electrical characteristics ? (t amb = 25 c, unless otherwise specified) parameter test conditions/remarks symbol min. typ. max. unit protection paths number of li nes which can be protected n channel - - 1 lines reverse stand-off voltage max. reverse working voltage v rwm --5.5v reverse voltage at i r = 0.1 a v r 5.5 - - v reverse current at v rwm = 5.5 v i r --0.1a reverse breakdown voltage at i r = 1 ma v br 6.0 8.8 10 v reverse clamping voltage at i pp = 1 a v c - 12.5 14 v at i pp = i ppm = 2.5 a v c -1618v capacitance at v r = 0 v; f = 1 mhz c d - 0.55 0.8 pf at v r = 3.3 v; f = 1 mhz c d -0.55- pf 0 % 20 % 40 % 60 % 80 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 80 90 100 time (ns) discharge current i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 80 % 100 % 010203040 time (s) i ppm 20 s to 50 % 8 s to 100 % 20548 v r (v) c d (pf) 0.7 0.6 0.8 0.4 0.5 0.2 0.3 0.0 0.1 0 1 2 3 4 5 f = 1mhz pin 1-2 or pin 2-1 22702 8 9 10 5 6 7 2 3 4 0 1 0.01 0.1 1 10 100 1000 10 000 v r (v) 22703 pin 1-2 or pin 2-1 i r in a
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 3 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - typical peak clamping voltage v c vs. peak pulse current i pp fig. 6 - typical clamping perf ormance at 8 kv contact discharge (acc. iec 61000-4-2) fig. 7 - typical clamping performance at esd contact discharge (acc. iec 61000-4-2) at 30 ns fig. 8 - typical attenuation in a 50 ?? system fig. 9 - typical diode impedance vs. frequency v c (v) i pp (a) 22704 14 16 18 10 12 14 4 6 8 0 2 0 1 2 3 pin 1-2 or pin 2-1 mea s ured acc. to iec 61000-4-5 (8/20 s - wave form) v c t (n s ) v c-e s d (v) 22705 10 120 140 +8k 60 80 10 20 40 -20 0 -10 0 10 20 30 40 50 60 70 80 90 pin 1-2 or pin 2-1 +8 kv acc. iec 61000-4-2 contact di s charge v e s d (kv) v c-e s d (v) 22706 0 10 20 30 40 50 60 70 051015 v c-e s d 30 n s acc. iec 61000-4-2 contact di s charge pin 1-2 or pin 2-1 -5 db -4 db -3 db -2 db -1 db 0 db 1.0e+07 1.0e+08 1.0e+09 pin 1-2 or pin 2-1 -5 v < v r < +5 v f (hz) / s 11/ 22707 1 10 100 1000 10 000 100 000 1.0e+07 1.0e+08 1.0e+09 pin 1-2 or pin 2-1 -5 v < v r < +5 v f (hz) impedance ( ) 22708
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 4 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package dimensions in millimeters (mils): clp0603-2l a1 e e b a d l e1 millimeter s a a1 b d e e min. nom. max. min. nom. max. 0.24 0.22 0.27 0.57 0.27 0.25 0.30 0.60 0.40 0.30 0.02 0.28 0.33 0.63 mil s 9.44 8.66 10.62 22.44 10.63 9.84 11.81 23.62 15.75 11.81 0.79 11.02 12.99 24.80 l 0.12 0.15 0.18 4.72 5.91 7.09 e1 0.25 9.84 foot print recommendation: s oldering ma s k opening 0.3 0.28 s older pad 0.75 0.28 0.05 0.05 created - date: 22. nov. 2010 document no.: s 8-v-3906.04-023 (4) 2 terminal leadle ss package (clp0603-2l) rev.3 - date: 14. s ept. 2011 22606 package = chip dimen s ion s in mm
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 5 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 carrier tape in millimeters: clp0603 orientation in carrier clp0603 a a-a s ection a 4 0.1 2 0.05 1.75 0.1 b b 8 + 0.3 - 0.1 b-b s ection 0.37 0.03 0.67 0.03 5 max. 2 0.33 0.03 0.2 0.02 ? 0.2 0.05 ? 1.55 0.05 3.5 0.05 cummulative tolerance s of 10 s procket hole s i s +/-0.2mm 22591 carrier tape s ipack tm 0603 document no. s 8-v-3906.04-0025 (4) created - date: 22. nov. 2010 clp0603 top view unreeling direction pin 1 a detail a 50:1 22607 orientation in carrier tape (clp0603) s 8-v-3906.04-026 (4) 22.10.2010
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 6 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 application note 1. pcb footprint design verified by internal tests, vishay recommends the soldering pad and solder mask opening desi gn as shown in fig. 1. we recommend using a non-sold er mask defined (nsmd) design, as shown below. the reason is that with a nsmd design, the size of the actual solder pad is more accurate (tolerances for copper etchings are smaller compared to a solder mask defined process). fig. 1 - recommended soldering pad design 2. pcb soldering pad metallization there are several common pa d metallization/finishes, including osp (organic solderab ility protectant), hasl (hot air solder level), and eniau. because of the clp0603s extremely small size, vishay only recommends using the electroless ni/immersion gol d over copper pad plating. 3. screen print process the solder paste is applied to the pcb by using a screen print process. the recommended stencil thickness for the clp0603 package is 80 m (the absolute maximum is 100 m). the recommended di mensions for the stencil openings are 12 mil (300 m) by 8 mil (200 m) for both pads. the side wall of the st encil openings should be tapered approximately 5 degrees. an electro-polished finish will support a better release of the paste. ? ? ? ? ? fig. 2 - maximum stencil openings - for a stencil thickness of 80 m note ? a wider stencil opening will result in a better solder paste release from the stencil. so the best qua lity can be obtained by using the optimum between the stencil quality, thickness, and opening. ? ? if a tilting of the package is observed, the amount of solder paste should be reduced slight ly. please also take into consideration the direct relation between the amount of solder paste and the package shear strength. 4. solder paste type type 4 solder pastes (or smaller powder sizes) are recommended. in our evaluation we used the cookson electronics alpha om-338 c sp (96.5 % sn/3 % ag/0.5 % cu) solder paste. 5. reflow soldering process a standard surface-mo unt reflow soldering process can be used (reference: jpc/jedec j-std-020d). however, for an optimum proc ess, recommendations from the solder paste supplier should be considered. variations in chemistry and viscosity of th e fluxer may require small adjustments to the soldering profile. ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.3 0.28 s oldering ma s k opening s older pad 0.75 0.28 0.05 0.05
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 7 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) tolerance for peak profile temperature (t p ) is defined as a supplier minimum and user maximum (2) tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and user maximum ? notes 1. all temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly r eflow (e.g. live-bug). if parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e. dead-bug). t p shall be within 2 c of the live-bug t p and still meet the t c requirements, otherwise, the profile shall be adjusted to achieve the latter. to accurately measure actual peak package bo dy temperatures refer to jep140 for the reco mmended thermo couple use. 2. reflow profiles in this document are for classification/precon ditioning and are not meant to specify board assembly profiles. actual board assembly profiles should be developed based on spec ific process needs and boar d designs and should not exceed the parameters in table 1. for example, if t c is 260 c and time t p is 30 s, this means the followin g for the supplier and the user: ? - for a supplier: the peak temperature must be at leas t 260 c. the time above 255 c must be at least 30 s. ? - for a user: the peak te mperature must not exceed 260 c. the time above 255 c must not exceed 30 s. 3. all components in the test load shall meet the classification profile requirements. 4. smd packages classified to a given moisture sensitivity level by using procedures or criteria defined within any previous ver sion of j-std-020, jesd22-a112 (rescinded), ipc-sm- 786 (rescinded) do not need to be reclassified to the cu rrent revision unless a chan ge in classification level or a higher peak classification temperature is desired. table 1 - classification reflow profiles profile feature snpb eutectic assembly lead (pb)-free assembly preheat and soak temperature min. (t smin. ) 100 c 150 c temperature max. (t smax. ) 150 c 200 c time (t smin. to t smax. ) (t s ) 60 s to 120 s 60 s to 120 s average ramp-up rate (t smax. to t p ) 3 c/s maximum liquidous temperature (t l ) 183 c 217 c time to liquidous (t l ) 60 s to 150 s 60 s to 150 s peak package temperature (t p ) (1) see classification temperature in table 3 see classification temperature in table 4 time (t p ) (2) with 5 c of the specified classification temperature (t c ) 20 s (2) 30 s (2) average ramp-down rate (t p to t smax. ) 6 c/s maximum time 25 c to peak temperature 6 min maximum 8 min maximum time temperature t s time 25 c to peak t p t p t l t smin. 25 t l t smax. preheat area t c - 5 c max. ramp up rate = 3 c/s max. ramp down rate = 6 c/s user t p supplier t p t c - 5 c t c supplier t p t c user t p t c
vbus05a1-sd0 www.vishay.com vishay semiconductors rev. 1.0, 09-jul-13 8 document number: 85245 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes 5. at the direction of the device manufactu rer, but not the board assembler/user, the maximum peak package body temperature (t p ) can exceed the values specified in tables 2 and 3. the use of a higher t p does not change the classification temperature (t c ). 6. package volume excludes external terminals (e.g., balls , bumps, lands, leads) and/ or nonintegral heat sinks. 7. the maximum component temperature reached during reflow depend s on package thickness and volume. the use on convection reflow processes reduces the thermal gradients between packages. however thermal gradients due to differences in thermal mass of smd packages may still exist. 8. moisture sensitivity levels of components intended for use in a lead (pb)-free assembly process shall be evaluated using the lead (pb)-free classification temperatures and profiles defined in table 1 and 3, whether or not lead (pb)-free. 9. smd packages classified to a given moisture sensitivity level by using procedures or criteria defined within any previous ver sion of j-std-020, jesd22-a112 (rescinded), ipc-sm- 786 (rescinded) do not need to be reclassified to the cu rrent revision unless a chan ge in classification level or a higher peak classification temperature is desired. 6. soldering quality inispection an x-ray inspection system is re quired to find defects such as shorts between pads, open contacts, and voids within the solder. in addition, a visual inspection by microscope or camera (of appropria te magnification) can be used to inspect the sides of the solder joints for acceptable shape and molten solder. 7. shear test comparison the data below shows a comparison of shear strength after a reflow soldering process. 8. rework procedure for rework, the clp0603 package must be removed from the pcb if there is any issue with the solder joints. standard smt rework systems are recommended for this. due to the small size of the package, the rework system should be equipped with a prope r magnification aid. 9. interchangeability of the clp with a plastic package of the same size based on our studies, the cl p is 100 % compatible with plastic packages of the same size. table 2 - snpb eutectic process - classification temperatures (t c ) package thickness volume mm 3 < 350 volume mm 3 ? 350 < 2.5 mm 235 c 220 c ? 2.5 mm 220 c 220 c table 3 - lead (pb)-free process - classification temperatures (t c ) package thickness volume mm 3 < 350 volume mm 3 350 to 2000 volume mm 3 > 2000 < 1.6 mm 260 c 260 c 260 c 1.6 mm to 2.5 mm 260 c 250 c 245 c > 2.5 mm 250 c 245 c 245 c vishay competitor 1 competitor 2 competitor 3 typical shear strength 500 g 350 g 600 g 440 g
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.
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